sdk-core v2026.11.05
PS2 SDK - core tier (build-critical EE/IOP modules)
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dma_registers.h File Reference
core/dma
#include <tamtypes.h>

Go to the source code of this file.

Macros

#define DMA_REG_CTRL   (volatile u32 *)0x1000E000
#define DMA_REG_STAT   (volatile u32 *)0x1000E010
#define DMA_REG_PCR   (volatile u32 *)0x1000E020
#define DMA_REG_SQWC   (volatile u32 *)0x1000E030
#define DMA_REG_RBSR   (volatile u32 *)0x1000E040
#define DMA_REG_RBOR   (volatile u32 *)0x1000E050
#define DMA_REG_STADR   (volatile u32 *)0x1000E060
#define DMA_REG_ENABLER   (volatile u32 *)0x1000F520
#define DMA_REG_ENABLEW   (volatile u32 *)0x1000F590
#define DMAE_DISABLE   0
#define DMAE_ENABLE   1
#define RELE_OFF   0
#define RELE_ON   1
#define MFD_OFF   0
#define MFD_RES   1
#define MFD_VIF   2
#define MFD_GIF   3
#define STS_UNSPEC   0
#define STS_SIF   1
#define STS_SPR   2
#define STS_IPU   3
#define STD_OFF   0
#define STD_VIF   1
#define STD_GIF   2
#define STD_SIF   3
#define RCYC_8   0
#define RCYC_16   1
#define RCYC_32   2
#define RCYC_64   3
#define RCYC_128   4
#define RCYC_256   5
#define DMA_SET_CTRL(DMAE, RELE, MFD, STS, STD, RCYC)
#define DMA_SET_STAT(CIS, SIS, MEIS, BEIS, CIM, SIM, MEIM)
#define DMA_SET_PCR(CPCOND, CDE, PCE)
#define DMA_SET_SQWC(SQWC, TQWC)
#define DMA_SET_RBOR(ADDR)
#define DMA_SET_RBSR(RMSK)
#define DMA_SET_STADR(ADDR)
#define DMA_SET_ENABLEW(A)
#define DMA_SET_ENABLER(A)
#define DMA_SET_CHCR(DIR, MODE, ASP, TTE, TIE, STR, TAG)
#define DMA_SET_MADR(ADDR, SPR)
#define DMA_SET_TADR(ADDR, SPR)
#define DMA_SET_ASR0(ADDR, SPR)
#define DMA_SET_ASR1(ADDR, SPR)
#define DMA_SET_SADR(ADDR)
#define DMA_SET_QWC(QWC)

Detailed Description

DMA registers

Definition in file dma_registers.h.

Macro Definition Documentation

◆ DMA_REG_CTRL

#define DMA_REG_CTRL   (volatile u32 *)0x1000E000

DMA Control Register

Definition at line 23 of file dma_registers.h.

◆ DMA_REG_ENABLER

#define DMA_REG_ENABLER   (volatile u32 *)0x1000F520

DMA Hold State Register

Definition at line 37 of file dma_registers.h.

◆ DMA_REG_ENABLEW

#define DMA_REG_ENABLEW   (volatile u32 *)0x1000F590

DMA Hold Control Register

Definition at line 39 of file dma_registers.h.

◆ DMA_REG_PCR

#define DMA_REG_PCR   (volatile u32 *)0x1000E020

Priority Control Register

Definition at line 27 of file dma_registers.h.

◆ DMA_REG_RBOR

#define DMA_REG_RBOR   (volatile u32 *)0x1000E050

Ring Buffer Address Register

Definition at line 33 of file dma_registers.h.

◆ DMA_REG_RBSR

#define DMA_REG_RBSR   (volatile u32 *)0x1000E040

Ring Buffer Size Register

Definition at line 31 of file dma_registers.h.

◆ DMA_REG_SQWC

#define DMA_REG_SQWC   (volatile u32 *)0x1000E030

Interleave Size Register

Definition at line 29 of file dma_registers.h.

◆ DMA_REG_STADR

#define DMA_REG_STADR   (volatile u32 *)0x1000E060

Stall Address Register

Definition at line 35 of file dma_registers.h.

◆ DMA_REG_STAT

#define DMA_REG_STAT   (volatile u32 *)0x1000E010

Interrupt Status Register

Definition at line 25 of file dma_registers.h.

◆ DMA_SET_ASR0

#define DMA_SET_ASR0 ( ADDR,
SPR )
Value:
(u32)((ADDR) & 0x7FFFFFFF) << 0 | (u32)((SPR) & 0x00000001) << 31

Definition at line 116 of file dma_registers.h.

◆ DMA_SET_ASR1

#define DMA_SET_ASR1 ( ADDR,
SPR )
Value:
(u32)((ADDR) & 0x7FFFFFFF) << 0 | (u32)((SPR) & 0x00000001) << 31

Definition at line 119 of file dma_registers.h.

◆ DMA_SET_CHCR

#define DMA_SET_CHCR ( DIR,
MODE,
ASP,
TTE,
TIE,
STR,
TAG )
Value:
(u32)((DIR) & 0x00000001) << 0 | (u32)((MODE) & 0x00000003) << 2 | \
(u32)((ASP) & 0x00000003) << 4 | (u32)((TTE ) & 0x00000001) << 6 | \
(u32)((TIE) & 0x00000001) << 7 | (u32)((STR ) & 0x00000001) << 8 | \
(u32)((TAG) & 0x0000FFFF) << 16
DIR
Definition ff.h:245

Per-dma channel registers

Definition at line 104 of file dma_registers.h.

◆ DMA_SET_CTRL

#define DMA_SET_CTRL ( DMAE,
RELE,
MFD,
STS,
STD,
RCYC )
Value:
(u32)(A & 0x00000001) << 0 | (u32)(RELE & 0x00000001) << 1 | \
(u32)(MFD & 0x00000003) << 2 | (u32)(STS & 0x00000003) << 4 | \
(u32)(STD & 0x00000003) << 6 | (u32)(RCYC & 0x00000007) << 8

Definition at line 75 of file dma_registers.h.

◆ DMA_SET_ENABLER

#define DMA_SET_ENABLER ( A)
Value:
(u32)((A) & 0x00000001) << 16

Definition at line 101 of file dma_registers.h.

◆ DMA_SET_ENABLEW

#define DMA_SET_ENABLEW ( A)
Value:
(u32)((A) & 0x00000001) << 16

Definition at line 99 of file dma_registers.h.

◆ DMA_SET_MADR

#define DMA_SET_MADR ( ADDR,
SPR )
Value:
(u32)((ADDR) & 0x7FFFFFFF) << 0 | (u32)((SPR) & 0x00000001) << 31

Definition at line 110 of file dma_registers.h.

◆ DMA_SET_PCR

#define DMA_SET_PCR ( CPCOND,
CDE,
PCE )
Value:
(u32)((CPCOND) & 0x000003FF) << 0 | (u32)((CDE) & 0x000003FF) << 16 | \
(u32)((PCE) & 0x00000001) << 31

Definition at line 86 of file dma_registers.h.

◆ DMA_SET_QWC

#define DMA_SET_QWC ( QWC)
Value:
(u32)((QWC) & 0x0000FFFF)

Definition at line 124 of file dma_registers.h.

◆ DMA_SET_RBOR

#define DMA_SET_RBOR ( ADDR)
Value:
(u32)((ADDR) & 0x00007FFF)

Definition at line 93 of file dma_registers.h.

◆ DMA_SET_RBSR

#define DMA_SET_RBSR ( RMSK)
Value:
(u32)((RMSK) & 0x00007FFF)

Definition at line 95 of file dma_registers.h.

◆ DMA_SET_SADR

#define DMA_SET_SADR ( ADDR)
Value:
(u32)((ADDR) & 0x00003FFF)

Definition at line 122 of file dma_registers.h.

◆ DMA_SET_SQWC

#define DMA_SET_SQWC ( SQWC,
TQWC )
Value:
(u32)((SQWC) & 0x000000FF) << 0 | (u32)((TQWC) & 0x000000FF) << 16

Definition at line 90 of file dma_registers.h.

◆ DMA_SET_STADR

#define DMA_SET_STADR ( ADDR)
Value:
(u32)((ADDR) & 0x00007FFF)

Definition at line 97 of file dma_registers.h.

◆ DMA_SET_STAT

#define DMA_SET_STAT ( CIS,
SIS,
MEIS,
BEIS,
CIM,
SIM,
MEIM )
Value:
(u32)((CIS) & 0x000003FF) << 0 | (u32)((SIS) & 0x00000001) << 13 | \
(u32)((MEIS) & 0x00000001) << 14 | (u32)((BEIS) & 0x00000001) << 15 | \
(u32)((CIM) & 0x000003FF) << 16 | (u32)((SIM) & 0x00000001) << 29 | \
(u32)((MEIM) & 0x00000001) << 30

Definition at line 80 of file dma_registers.h.

◆ DMA_SET_TADR

#define DMA_SET_TADR ( ADDR,
SPR )
Value:
(u32)((ADDR) & 0x7FFFFFFF) << 0 | (u32)((SPR) & 0x00000001) << 31

Definition at line 113 of file dma_registers.h.

◆ DMAE_DISABLE

#define DMAE_DISABLE   0

Enable DMA Controller

Definition at line 42 of file dma_registers.h.

◆ DMAE_ENABLE

#define DMAE_ENABLE   1

Definition at line 43 of file dma_registers.h.

◆ MFD_GIF

#define MFD_GIF   3

Definition at line 53 of file dma_registers.h.

◆ MFD_OFF

#define MFD_OFF   0

fifo drain?

Definition at line 50 of file dma_registers.h.

◆ MFD_RES

#define MFD_RES   1

Definition at line 51 of file dma_registers.h.

◆ MFD_VIF

#define MFD_VIF   2

Definition at line 52 of file dma_registers.h.

◆ RCYC_128

#define RCYC_128   4

Definition at line 72 of file dma_registers.h.

◆ RCYC_16

#define RCYC_16   1

Definition at line 69 of file dma_registers.h.

◆ RCYC_256

#define RCYC_256   5

Definition at line 73 of file dma_registers.h.

◆ RCYC_32

#define RCYC_32   2

Definition at line 70 of file dma_registers.h.

◆ RCYC_64

#define RCYC_64   3

Definition at line 71 of file dma_registers.h.

◆ RCYC_8

#define RCYC_8   0

Cycles to release control

Definition at line 68 of file dma_registers.h.

◆ RELE_OFF

#define RELE_OFF   0

Enable Cycle Stealing

Definition at line 46 of file dma_registers.h.

◆ RELE_ON

#define RELE_ON   1

Definition at line 47 of file dma_registers.h.

◆ STD_GIF

#define STD_GIF   2

Definition at line 64 of file dma_registers.h.

◆ STD_OFF

#define STD_OFF   0

stall drain?

Definition at line 62 of file dma_registers.h.

◆ STD_SIF

#define STD_SIF   3

Definition at line 65 of file dma_registers.h.

◆ STD_VIF

#define STD_VIF   1

Definition at line 63 of file dma_registers.h.

◆ STS_IPU

#define STS_IPU   3

Definition at line 59 of file dma_registers.h.

◆ STS_SIF

#define STS_SIF   1

Definition at line 57 of file dma_registers.h.

◆ STS_SPR

#define STS_SPR   2

Definition at line 58 of file dma_registers.h.

◆ STS_UNSPEC

#define STS_UNSPEC   0

stall source?

Definition at line 56 of file dma_registers.h.