sdk-core v2026.11.05
PS2 SDK - core tier (build-critical EE/IOP modules)
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ps2atad.c
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1/*
2# _____ ___ ____ ___ ____
3# ____| | ____| | | |____|
4# | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
5#-----------------------------------------------------------------------
6# Copyright (c) 2003 Marcus R. Brown <mrbrown@0xd6.org>
7# Licenced under Academic Free License version 2.0
8# Review ps2sdk README & LICENSE files for further details.
9*/
10
21
22#include <types.h>
23#include <defs.h>
24#include <irx.h>
25#include <loadcore.h>
26#include <thbase.h>
27#include <thevent.h>
28#include <stdio.h>
29#include <sysclib.h>
30#ifdef ATA_USE_DEV9
31#include <dev9.h>
32#endif
33#ifdef ATA_USE_AIFDEV9
34#include <aifdev9.h>
35#endif
36#include <atad.h>
37#ifdef ATA_ENABLE_BDM
38#include <bdm.h>
39#include <errno.h>
40#endif
41
42#ifdef ATA_USE_DEV9
43#include <speedregs.h>
44#endif
45#include <atahw.h>
46
47#define MODNAME "atad"
48// TODO: last sdk 3.1.0 has ATAD module version 2.9 with significant changes.
49// Check what was changed, and maybe port changes.
50// CRC32: C2337807
51IRX_ID(MODNAME, 2, 7);
52
53#define M_PRINTF(format, args...) \
54 printf(MODNAME ": " format, ##args)
55
56#define BANNER "ATA device driver %s - Copyright (c) 2003 Marcus R. Brown\n"
57#define VERSION "v1.2"
58
59#define ATA_XFER_MODE_PIO 0x08
60#ifdef ATA_MWDMA_MODES
61#define ATA_XFER_MODE_MDMA 0x20
62#endif
63#define ATA_XFER_MODE_UDMA 0x40
64
65#define ATA_EV_TIMEOUT 1
66#define ATA_EV_COMPLETE 2
67
68static int ata_devinfo_init = 0;
69static int ata_evflg = -1;
70
71// Workarounds
72static u8 ata_dvrp_workaround = 0; // Please read the comments in _start().
73#ifdef ATA_USE_DEV9
74#ifdef ATA_GAMESTAR_WORKAROUND
75static u8 ata_gamestar_workaround = 0;
76#endif
77#endif
78
79/* Local device info kept for drives 0 and 1. */
80static ata_devinfo_t atad_devinfo[2];
81
82/* Data returned from DEVICE IDENTIFY is kept here. Also, this is used by the
83 security commands to set and unlock the password. */
84static u16 ata_param[256];
85
86/* ATA command info. */
87typedef struct _ata_cmd_info
88{
89 u8 command;
90 u8 type;
91} ata_cmd_info_t;
92
93static const ata_cmd_info_t ata_cmd_table[] = {
94 {ATA_C_NOP, 1},
95 {ATA_C_CFA_REQUEST_EXTENDED_ERROR_CODE, 1},
96 {ATA_C_DEVICE_RESET, 5},
97 {ATA_C_READ_SECTOR, 2},
98 {ATA_C_READ_SECTOR_EXT, 0x82},
99 {ATA_C_READ_DMA_EXT, 0x84},
100 {ATA_C_READ_NATIVE_MAX_ADDRESS_EXT, 0x81},
101 {ATA_C_READ_MULTIPLE_EXT, 0x82},
102 {ATA_C_WRITE_SECTOR, 3},
103 {ATA_C_WRITE_LONG, 8},
104 {ATA_C_WRITE_SECTOR_EXT, 0x83},
105 {ATA_C_WRITE_DMA_EXT, 0x84},
106 {ATA_C_SET_MAX_ADDRESS_EXT, 0x81},
107 {ATA_C_CFA_WRITE_SECTORS_WITHOUT_ERASE, 3},
108 {ATA_C_WRITE_MULTIPLE_EXT, 0x83},
109 {ATA_C_READ_VERIFY_SECTOR, 1},
110 {ATA_C_READ_VERIFY_SECTOR_EXT, 0x81},
111 {ATA_C_SEEK, 1},
112 {ATA_C_CFA_TRANSLATE_SECTOR, 2},
113 {ATA_C_SCE_SECURITY_CONTROL, 7},
114 {ATA_C_EXECUTE_DEVICE_DIAGNOSTIC, 6},
115 {ATA_C_INITIALIZE_DEVICE_PARAMETERS, 1},
116 {ATA_C_DOWNLOAD_MICROCODE, 3},
117 {ATA_C_IDENTIFY_PACKET_DEVICE, 2},
118 {ATA_C_SMART, 7},
119 {ATA_C_CFA_ERASE_SECTORS, 1},
120 {ATA_C_READ_MULTIPLE, 2},
121 {ATA_C_WRITE_MULTIPLE, 3},
122 {ATA_C_SET_MULTIPLE_MODE, 1},
123 {ATA_C_READ_DMA, 4},
124 {ATA_C_WRITE_DMA, 4},
125 {ATA_C_CFA_WRITE_MULTIPLE_WITHOUT_ERASE, 3},
126 {ATA_C_GET_MEDIA_STATUS, 1},
127 {ATA_C_MEDIA_LOCK, 1},
128 {ATA_C_MEDIA_UNLOCK, 1},
129 {ATA_C_STANDBY_IMMEDIATE, 1},
130 {ATA_C_IDLE_IMMEDIATE, 1},
131 {ATA_C_STANDBY, 1},
132 {ATA_C_IDLE, 1},
133 {ATA_C_READ_BUFFER, 2},
134 {ATA_C_CHECK_POWER_MODE, 1},
135 {ATA_C_SLEEP, 1},
136 {ATA_C_FLUSH_CACHE, 1},
137 {ATA_C_WRITE_BUFFER, 3},
138 {ATA_C_FLUSH_CACHE_EXT, 1},
139 {ATA_C_IDENTIFY_DEVICE, 2},
140 {ATA_C_MEDIA_EJECT, 1},
141 {ATA_C_SET_FEATURES, 1},
142 {ATA_C_SECURITY_SET_PASSWORD, 3},
143 {ATA_C_SECURITY_UNLOCK, 3},
144 {ATA_C_SECURITY_ERASE_PREPARE, 1},
145 {ATA_C_SECURITY_ERASE_UNIT, 3},
146 {ATA_C_SECURITY_FREEZE_LOCK, 1},
147 {ATA_C_SECURITY_DISABLE_PASSWORD, 3},
148 {ATA_C_READ_NATIVE_MAX_ADDRESS, 1},
149 {ATA_C_SET_MAX_ADDRESS, 1}};
150#define ATA_CMD_TABLE_SIZE (sizeof ata_cmd_table / sizeof(ata_cmd_info_t))
151
152static const ata_cmd_info_t sec_ctrl_cmd_table[] = {
153 {ATA_SCE_IDENTIFY_DRIVE, 2},
154 {ATA_SCE_SECURITY_ERASE_PREPARE, 1},
155 {ATA_SCE_SECURITY_ERASE_UNIT, 1},
156 {ATA_SCE_SECURITY_FREEZE_LOCK, 1},
157 {ATA_SCE_SECURITY_SET_PASSWORD, 3},
158 {ATA_SCE_SECURITY_UNLOCK, 3},
159 {ATA_SCE_SECURITY_WRITE_ID, 3},
160 {ATA_SCE_SECURITY_READ_ID, 2}};
161#define SEC_CTRL_CMD_TABLE_SIZE (sizeof sec_ctrl_cmd_table / sizeof(ata_cmd_info_t))
162
163static const ata_cmd_info_t smart_cmd_table[] = {
164 {ATA_S_SMART_READ_DATA, 2},
165 {ATA_S_SMART_ENABLE_DISABLE_AUTOSAVE, 1},
166 {ATA_S_SMART_SAVE_ATTRIBUTE_VALUES, 1},
167 {ATA_S_SMART_EXECUTE_OFF_LINE, 1},
168 {ATA_S_SMART_READ_LOG, 2},
169 {ATA_S_SMART_WRITE_LOG, 3},
170 {ATA_S_SMART_ENABLE_OPERATIONS, 1},
171 {ATA_S_SMART_DISABLE_OPERATIONS, 1},
172 {ATA_S_SMART_RETURN_STATUS, 1}};
173#define SMART_CMD_TABLE_SIZE (sizeof smart_cmd_table / sizeof(ata_cmd_info_t))
174
175/* This is the state info tracked between sceAtaExecCmd() and sceAtaWaitResult(). */
176typedef struct _ata_cmd_state
177{
178 s32 type; /* The ata_cmd_info_t type field. */
179 union
180 {
181 void *buf;
182 u8 *buf8;
183 u16 *buf16;
184 };
185 u32 blkcount; /* The number of 512-byte blocks (sectors) to transfer. */
186 s32 dir; /* DMA direction: 0 - to RAM, 1 - from RAM. */
187} ata_cmd_state_t;
188
189static ata_cmd_state_t atad_cmd_state;
190
191#ifdef ATA_ENABLE_BDM
192#define NUM_DEVICES 2
193#define ATA_BD_SECTOR_SIZE 512
194static struct block_device g_ata_bd[NUM_DEVICES];
195#endif
196
197#ifdef ATA_USE_DEV9
198static int ata_intr_cb(int flag);
199#endif
200#ifdef ATA_USE_AIFDEV9
201static int ata_intr_cb(void);
202#endif
203static unsigned int ata_alarm_cb(void *unused);
204
205#ifdef ATA_USE_AIFDEV9
206static void aif_tune_drive(int unit, int mode);
207#endif
208
209#ifdef ATA_USE_DEV9
210static void ata_set_dir(int dir);
211
212static void ata_pio_mode(int mode);
213#ifdef ATA_MWDMA_MODES
214static void ata_multiword_dma_mode(int mode);
215#endif
216static void ata_ultra_dma_mode(int mode);
217#endif
218static void ata_shutdown_cb(void);
219
220int ata_device_sector_io64(int device, void *buf, u64 lba, u32 nsectors, int dir);
221
222#ifdef ATA_ENABLE_BDM
223static int ata_bd_read(struct block_device *bd, u64 sector, void *buffer, u16 count);
224static int ata_bd_write(struct block_device *bd, u64 sector, const void *buffer, u16 count);
225static void ata_bd_flush(struct block_device *bd);
226static int ata_bd_stop(struct block_device *bd);
227#endif
228
229extern struct irx_export_table _exp_atad;
230
231#ifdef ATA_USE_DEV9
232// In v1.04, DMA was enabled in ata_set_dir() instead.
233static void ata_pre_dma_cb(int bcr, int dir)
234{
235 USE_SPD_REGS;
236
237 (void)bcr;
238 (void)dir;
239
240 SPD_REG16(SPD_R_XFR_CTRL) |= 0x80;
241}
242
243static void ata_post_dma_cb(int bcr, int dir)
244{
245 USE_SPD_REGS;
246
247 (void)bcr;
248 (void)dir;
249
250 SPD_REG16(SPD_R_XFR_CTRL) &= ~0x80;
251}
252#endif
253
254static int ata_create_event_flag(void)
255{
256 iop_event_t event;
257
258 event.attr = EA_SINGLE; // In v1.04, EA_MULTI was specified.
259 event.bits = 0;
260 return CreateEventFlag(&event);
261}
262
263int _start(int argc, char *argv[])
264{
265#ifdef ATA_USE_DEV9
266 USE_SPD_REGS;
267#endif
268#ifdef ATA_USE_AIFDEV9
269 USE_AIF_REGS;
270#endif
271 int res;
272
273 (void)argc;
274 (void)argv;
275
276 printf(BANNER, VERSION);
277
278 res = MODULE_NO_RESIDENT_END;
279
280#ifdef ATA_USE_DEV9
281 if (!(SPD_REG16(SPD_R_REV_3) & SPD_CAPS_ATA) || !(SPD_REG16(SPD_R_REV_8) & 0x02)) {
282 M_PRINTF("HDD is not connected, exiting.\n");
283 goto out;
284 }
285
286 /* The PSX (Not the PlayStation or PSOne, but a PS2 with a DVR unit) has got an extra processor (Fujitsu MB91302A, aka the "DVRP") that seems to be emulating the console's PS2 ATA interface.
287 The stock disks of all PSX units are definitely 48-bit LBA compliant because of their capacities, but the DVRP's emulation seems to have a design problem:
288 1. It indicates that 48-bit LBA is supported.
289 2. The 48-bit LBA capacity fields show the true capacity of the disk.
290 3. Accesses to beyond the 28-bit LBA capacity (Which is 40.000GB by default) will result in I/O errors.
291 4. (For some PSX units like the DESR-7500): Double-writes to the ATA registers seem to cause the ATA interface to stall.
292
293 The problem is obviously in the DVRP's firmware, but we currently have no way to fix these bugs because the DVRP is even more heavily secured that the IOP.
294 In the eyes of Sony, there isn't a problem because none of their retail PlayStation 2 software ever supported 48-bit LBA.
295
296 The workaround here is to return the 28-bit LBA as the total size and only use 48-bit LBA commands when required. */
297 ata_dvrp_workaround = (SPD_REG16(SPD_R_REV_3) & SPD_CAPS_DVR) ? 1 : 0;
298#endif
299
300#ifdef ATA_USE_AIFDEV9
301 if (!aifIsDetected()) {
302 M_PRINTF("AIF HDD: controller not found.\n");
303 goto out;
304 }
305 aif_regs[AIF_ATA_TCFG] = 0; // Clear ATA timing configuration.
306#endif
307
308#ifdef ATA_USE_DEV9
309#ifdef ATA_GAMESTAR_WORKAROUND
310 /* Some compatible adaptors may malfunction if transfers are not done according to the old ps2atad design.
311 Official adaptors appear to have a 0x0001 set for this register, but not compatibles.
312 While official I/O to this register are 8-bit, some compatibles have a 0x01 for the lower 8-bits,
313 but the upper 8-bits contain some random value. Hence perform a 16-bit read instead. */
314 ata_gamestar_workaround = (SPD_REG16(0x20) != 1) ? 1 : 0;
315 if (ata_gamestar_workaround) {
316 M_PRINTF("Compatible adaptor detected.\n");
317 /* Reportedly, some compatible adapters output more than SPD_CAPS_SMAP | SPD_CAPS_ATA | SPD_CAPS_UART in the SPD_R_REV_3 register. */
318 /* https://github.com/regttycomit/PS2_CXD9731_HDD_ADAPTOR/blob/7a6d058019f932eb701ced3bddca6c7eda498b50/hdl/chip.v#L506 */
319 ata_dvrp_workaround = 0;
320 }
321#endif
322#endif
323
324 if ((ata_evflg = ata_create_event_flag()) < 0) {
325 M_PRINTF("Couldn't create event flag, exiting.\n");
326 goto out;
327 }
328
329#ifdef ATA_USE_DEV9
330 /* In v1.04, PIO mode 0 was set here. In late versions, it is set in ata_init_devices(). */
331 SpdRegisterIntrHandler(1, &ata_intr_cb);
332 SpdRegisterIntrHandler(0, &ata_intr_cb);
333#ifdef ATA_GAMESTAR_WORKAROUND
334 if (!ata_gamestar_workaround) {
335#endif
336 dev9RegisterPreDmaCb(0, &ata_pre_dma_cb);
337 dev9RegisterPostDmaCb(0, &ata_post_dma_cb);
338#ifdef ATA_GAMESTAR_WORKAROUND
339 }
340#endif
341 /* Register this at the last position, as it should be the last thing done before shutdown. */
342 Dev9RegisterPowerOffHandler(15, &ata_shutdown_cb);
343#endif
344
345#ifdef ATA_USE_AIFDEV9
346 aifRegisterIntrCb(AIF_INUM_ATA0, &ata_intr_cb);
347 aifRegisterShutdownCb(AIF_INUM_ATA0, &ata_shutdown_cb);
348
349 M_PRINTF("AIF HDD initialized.\n");
350#endif
351
352#ifdef ATA_ENABLE_BDM
353 {
354 int i;
355
356 for (i = 0; i < NUM_DEVICES; ++i) {
357 g_ata_bd[i].priv = (void *)&atad_devinfo[i];
358 g_ata_bd[i].name = "ata";
359 g_ata_bd[i].path = "ata";
360 g_ata_bd[i].devNr = i;
361 g_ata_bd[i].parNr = 0;
362 g_ata_bd[i].parId = 0x00;
363 g_ata_bd[i].sectorSize = 512;
364 g_ata_bd[i].sectorOffset = 0;
365 g_ata_bd[i].sectorCount = 0;
366
367 g_ata_bd[i].read = ata_bd_read;
368 g_ata_bd[i].write = ata_bd_write;
369 g_ata_bd[i].flush = ata_bd_flush;
370 g_ata_bd[i].stop = ata_bd_stop;
371 }
372 }
373
374 sceAtaInit(0);
375 sceAtaInit(1);
376#endif
377
378 if (RegisterLibraryEntries(&_exp_atad) != 0) {
379 M_PRINTF("Library is already registered, exiting.\n");
380 goto out;
381 }
382
383 res = MODULE_RESIDENT_END;
384 M_PRINTF("Driver loaded.\n");
385out:
386 return res;
387}
388
389int _exit(void) { return MODULE_RESIDENT_END; }
390
391#ifdef ATA_USE_DEV9
392static int ata_intr_cb(int flag)
393{
394 if (flag == 1) { /* New card, invalidate device info. */
395 memset(atad_devinfo, 0, sizeof atad_devinfo);
396 } else {
397 SpdIntrDisable(SPD_INTR_ATA);
398 iSetEventFlag(ata_evflg, ATA_EV_COMPLETE);
399 }
400
401 return 1;
402}
403#endif
404
405#ifdef ATA_USE_AIFDEV9
406static int ata_intr_cb(void)
407{
408 aifIntrDisable(AIF_INTR_ATA0);
409 iSetEventFlag(ata_evflg, ATA_EV_COMPLETE);
410
411 return 1;
412}
413#endif
414
415static unsigned int ata_alarm_cb(void *unused)
416{
417 (void)unused;
418
419 iSetEventFlag(ata_evflg, ATA_EV_TIMEOUT);
420 return 0;
421}
422
423/* Export 8 */
424int sceAtaGetError(void)
425{
426#ifdef ATA_USE_DEV9
427 USE_ATA_REGS;
428#endif
429#ifdef ATA_USE_AIFDEV9
430 USE_AIF_ATA_REGS;
431#endif
432 return ata_hwport->r_error & 0xff;
433}
434
435#define ATA_WAIT_BUSY 0x80
436#define ATA_WAIT_BUSBUSY 0x88
437
438#define ata_wait_busy() gen_ata_wait_busy(ATA_WAIT_BUSY)
439#define ata_wait_bus_busy() gen_ata_wait_busy(ATA_WAIT_BUSBUSY)
440
441/* 0x80 for busy, 0x88 for bus busy.
442 In the original ATAD, the busy and bus-busy functions were separate, but similar. */
443static int gen_ata_wait_busy(int bits)
444{
445#ifdef ATA_USE_DEV9
446 USE_ATA_REGS;
447#endif
448#ifdef ATA_USE_AIFDEV9
449 USE_AIF_ATA_REGS;
450#endif
451 int i, delay;
452
453 for (i = 0; i < 80; i++) {
454 int didx;
455
456 if (!(ata_hwport->r_control & bits))
457 return 0;
458
459 didx = i / 10;
460 switch (didx) {
461 case 0:
462 continue;
463 case 1:
464 delay = 100;
465 break;
466 case 2:
467 delay = 1000;
468 break;
469 case 3:
470 delay = 10000;
471 break;
472 case 4:
473 delay = 100000;
474 break;
475 default:
476 delay = 1000000;
477 }
478
479 DelayThread(delay);
480 }
481
482 M_PRINTF("Timeout while waiting on busy (0x%02x).\n", bits);
483 return ATA_RES_ERR_TIMEOUT;
484}
485
486static int ata_device_select(int device)
487{
488#ifdef ATA_USE_DEV9
489 USE_ATA_REGS;
490#endif
491#ifdef ATA_USE_AIFDEV9
492 USE_AIF_ATA_REGS;
493#endif
494 int res;
495
496 if ((res = ata_wait_bus_busy()) < 0)
497 return res;
498
499 /* If the device was already selected, nothing to do. */
500 if (((ata_hwport->r_select >> 4) & 1) == device)
501 return 0;
502
503 /* Select the device. */
504 ata_hwport->r_select = (device & 1) << 4;
505 (void)(ata_hwport->r_control);
506 (void)(ata_hwport->r_control); // Only done once in v1.04.
507
508 return ata_wait_bus_busy();
509}
510
511/* Export 6 */
512/*
513 28-bit LBA:
514 sector (7:0) -> LBA (7:0)
515 lcyl (7:0) -> LBA (15:8)
516 hcyl (7:0) -> LBA (23:16)
517 device (3:0) -> LBA (27:24)
518
519 48-bit LBA just involves writing the upper 24 bits in the format above into each respective register on the first write pass, before writing the lower 24 bits in the 2nd write pass. The LBA bits within the device field are not used in either write pass.
520*/
521int sceAtaExecCmd(void *buf, u32 blkcount, u16 feature, u16 nsector, u16 sector, u16 lcyl, u16 hcyl, u16 select, u16 command)
522{
523#ifdef ATA_USE_DEV9
524 USE_ATA_REGS;
525#endif
526#ifdef ATA_USE_AIFDEV9
527 USE_AIF_ATA_REGS;
528#endif
529 iop_sys_clock_t cmd_timeout;
530 const ata_cmd_info_t *cmd_table;
531 int i, res, type, cmd_table_size;
532 int using_timeout, device = (select >> 4) & 1;
533 u8 searchcmd;
534
535 ClearEventFlag(ata_evflg, 0);
536
537 if (!atad_devinfo[device].exists)
538 return ATA_RES_ERR_NODEV;
539
540 if ((res = ata_device_select(device)) != 0)
541 return res;
542
543 /* For the SCE and SMART commands, we need to search on the subcommand
544 specified in the feature register. */
545 if (command == ATA_C_SCE_SECURITY_CONTROL) {
546 cmd_table = sec_ctrl_cmd_table;
547 cmd_table_size = SEC_CTRL_CMD_TABLE_SIZE;
548 searchcmd = (u8)feature;
549 } else if (command == ATA_C_SMART) {
550 cmd_table = smart_cmd_table;
551 cmd_table_size = SMART_CMD_TABLE_SIZE;
552 searchcmd = (u8)feature;
553 } else {
554 cmd_table = ata_cmd_table;
555 cmd_table_size = ATA_CMD_TABLE_SIZE;
556 searchcmd = (u8)command;
557 }
558
559 type = 0;
560 for (i = 0; i < cmd_table_size; i++) {
561 if (searchcmd == cmd_table[i].command) {
562 type = cmd_table[i].type;
563 break;
564 }
565 }
566
567 if (!(atad_cmd_state.type = type & 0x7F)) // Non-SONY: ignore the 48-bit LBA flag.
568 return ATA_RES_ERR_CMD;
569
570 atad_cmd_state.buf = buf;
571 atad_cmd_state.blkcount = blkcount;
572
573 /* Check that the device is ready if this the appropiate command. */
574 if (!(ata_hwport->r_control & 0x40)) {
575 switch (command) {
576 case ATA_C_DEVICE_RESET:
577 case ATA_C_EXECUTE_DEVICE_DIAGNOSTIC:
578 case ATA_C_INITIALIZE_DEVICE_PARAMETERS:
579 case ATA_C_PACKET:
580 case ATA_C_IDENTIFY_PACKET_DEVICE:
581 break;
582 default:
583 M_PRINTF("Error: Device %d is not ready.\n", device);
584 return ATA_RES_ERR_NOTREADY;
585 }
586 }
587
588 /* Does this command need a timeout? */
589 using_timeout = 0;
590 switch (type & 0x7F) { // Non-SONY: ignore the 48-bit LBA flag.
591 case 1:
592 case 6:
593 using_timeout = 1;
594 break;
595 case 4:
596 atad_cmd_state.dir = (command != ATA_C_READ_DMA && command != ATA_C_READ_DMA_EXT);
597 using_timeout = 1;
598 break;
599 }
600
601 if (using_timeout) {
602 cmd_timeout.lo = 0x41eb0000;
603 cmd_timeout.hi = 0;
604
605 /* SECURITY ERASE UNIT needs a bit more time. */
606 if (command == ATA_C_SCE_SECURITY_CONTROL && feature == ATA_SCE_SECURITY_ERASE_UNIT)
607 USec2SysClock(180000000, &cmd_timeout);
608
609 if ((res = SetAlarm(&cmd_timeout, &ata_alarm_cb, NULL)) < 0)
610 return res;
611 }
612
613 /* Enable the command completion interrupt. */
614 if ((type & 0x7F) == 1) {
615#ifdef ATA_USE_DEV9
616 SpdIntrEnable(SPD_INTR_ATA0);
617#endif
618#ifdef ATA_USE_AIFDEV9
619 aifIntrEnable(AIF_INTR_ATA0);
620#endif
621 }
622
623 /* Finally! We send off the ATA command with arguments. */
624 ata_hwport->r_control = (using_timeout == 0) << 1;
625
626 if (type & 0x80) { // For the sake of achieving improved performance, write the registers twice only if required! This is also required for compatibility with the buggy firmware of certain PSX units.
627 /* 48-bit LBA requires writing to the address registers twice,
628 24 bits of the LBA address is written each time.
629 Writing to registers twice does not affect 28-bit LBA since
630 only the latest data stored in address registers is used. */
631 ata_hwport->r_feature = (feature >> 8) & 0xff;
632 ata_hwport->r_nsector = (nsector >> 8) & 0xff;
633 ata_hwport->r_sector = (sector >> 8) & 0xff;
634 ata_hwport->r_lcyl = (lcyl >> 8) & 0xff;
635 ata_hwport->r_hcyl = (hcyl >> 8) & 0xff;
636 }
637
638 ata_hwport->r_feature = feature & 0xff;
639 ata_hwport->r_nsector = nsector & 0xff;
640 ata_hwport->r_sector = sector & 0xff;
641 ata_hwport->r_lcyl = lcyl & 0xff;
642 ata_hwport->r_hcyl = hcyl & 0xff;
643 ata_hwport->r_select = (select | ATA_SEL_LBA) & 0xff; // In v1.04, LBA was enabled in the sceAtaDmaTransfer function.
644 ata_hwport->r_command = command & 0xff;
645
646#ifdef ATA_USE_DEV9
647 /* Turn on the LED. */
648 SpdSetLED(1);
649#endif
650
651 return 0;
652}
653
654/* Do a PIO transfer, to or from the device. */
655static int ata_pio_transfer(ata_cmd_state_t *cmd_state)
656{
657#ifdef ATA_USE_DEV9
658 USE_ATA_REGS;
659#endif
660#ifdef ATA_USE_AIFDEV9
661 USE_AIF_ATA_REGS;
662#endif
663 u16 *buf16;
664 int i, type;
665 u16 status = ata_hwport->r_status & 0xff;
666
667 if (status & ATA_STAT_ERR) {
668 M_PRINTF("Error: PIO cmd error: status 0x%02x, error 0x%02x.\n", status, sceAtaGetError());
669 return ATA_RES_ERR_IO;
670 }
671
672 /* DRQ must be set (data request). */
673 if (!(status & ATA_STAT_DRQ))
674 return ATA_RES_ERR_NODATA;
675
676 type = cmd_state->type;
677
678 if (type == 3 || type == 8) {
679 /* PIO data out */
680 buf16 = cmd_state->buf16;
681 for (i = 0; i < 256; i++) {
682 ata_hwport->r_data = *buf16;
683 cmd_state->buf16 = ++buf16;
684 }
685 if (cmd_state->type == 8) {
686 u8 *buf8;
687
688 buf8 = cmd_state->buf8;
689 for (i = 0; i < 4; i++) {
690 ata_hwport->r_data = *buf8;
691 cmd_state->buf8 = ++buf8;
692 }
693 }
694 } else if (type == 2) {
695 /* PIO data in */
696 buf16 = cmd_state->buf16;
697 for (i = 0; i < 256; i++) {
698 *buf16 = ata_hwport->r_data;
699 cmd_state->buf16 = ++buf16;
700 }
701 }
702
703 return 0;
704}
705
706#ifdef ATA_USE_DEV9
707/* Complete a DMA transfer, to or from the device. */
708static int ata_dma_complete(void *buf, u32 blkcount, int dir)
709{
710 USE_ATA_REGS;
711 USE_SPD_REGS;
712 u32 bits, count, nbytes;
713 int i, res;
714 u16 dma_stat;
715
716 while (blkcount) {
717 for (i = 0; i < 20; i++)
718 if ((dma_stat = SPD_REG16(0x38) & 0x1f))
719 goto next_transfer;
720
721 if (dma_stat)
722 goto next_transfer;
723
724 SpdIntrEnable(SPD_INTR_ATA);
725 /* Wait for the previous transfer to complete or a timeout. */
726 WaitEventFlag(ata_evflg, ATA_EV_TIMEOUT | ATA_EV_COMPLETE, WEF_CLEAR | WEF_OR, &bits);
727
728 if (bits & ATA_EV_TIMEOUT) { /* Timeout. */
729 M_PRINTF("Error: DMA timeout.\n");
730 return ATA_RES_ERR_TIMEOUT;
731 }
732 /* No DMA completion bit? Spurious interrupt. */
733 if (!(SPD_REG16(SPD_R_INTR_STAT) & 0x02)) {
734 if (ata_hwport->r_control & 0x01) {
735 M_PRINTF("Error: Command error while doing DMA.\n");
736 M_PRINTF("Error: Command error status 0x%02x, error 0x%02x.\n", ata_hwport->r_status, sceAtaGetError());
737 /* In v1.04, there was no check for ICRC. */
738 return ((sceAtaGetError() & ATA_ERR_ICRC) ? ATA_RES_ERR_ICRC : ATA_RES_ERR_IO);
739 } else {
740 M_PRINTF("Warning: Got command interrupt, but not an error.\n");
741 continue;
742 }
743 }
744
745 dma_stat = SPD_REG16(0x38) & 0x1f;
746
747 next_transfer:
748 count = (blkcount < dma_stat) ? blkcount : dma_stat;
749 nbytes = count * 512;
750 if ((res = SpdDmaTransfer(0, buf, (nbytes << 9) | 32, dir)) < 0)
751 return res;
752
753 buf = (void *)((u8 *)buf + nbytes);
754 blkcount -= count;
755 }
756
757 return 0;
758}
759#endif
760
761/* Export 7 */
762int sceAtaWaitResult(void)
763{
764#ifdef ATA_USE_DEV9
765 USE_SPD_REGS;
766 USE_ATA_REGS;
767#endif
768#ifdef ATA_USE_AIFDEV9
769 USE_AIF_ATA_REGS;
770#endif
771 ata_cmd_state_t *cmd_state = &atad_cmd_state;
772 u32 bits;
773 int res = 0, type = cmd_state->type;
774 u16 stat;
775
776 if (type == 1 || type == 6) { /* Non-data commands. */
777 WaitEventFlag(ata_evflg, ATA_EV_TIMEOUT | ATA_EV_COMPLETE, WEF_CLEAR | WEF_OR, &bits);
778 if (bits & ATA_EV_TIMEOUT) { /* Timeout. */
779 M_PRINTF("Error: ATA timeout on a non-data command.\n");
780 return ATA_RES_ERR_TIMEOUT;
781 }
782 } else if (type == 4) { /* DMA. */
783#ifdef ATA_USE_DEV9
784 int i;
785
786 if ((res = ata_dma_complete(cmd_state->buf, cmd_state->blkcount,
787 cmd_state->dir)) < 0)
788 goto finish;
789
790 for (i = 0; i < 100; i++)
791 if ((stat = SPD_REG16(SPD_R_INTR_STAT) & 0x01))
792 break;
793 if (!stat) {
794 SpdIntrEnable(SPD_INTR_ATA0);
795 WaitEventFlag(ata_evflg, ATA_EV_TIMEOUT | ATA_EV_COMPLETE, WEF_CLEAR | WEF_OR, &bits);
796 if (bits & ATA_EV_TIMEOUT) {
797 M_PRINTF("Error: ATA timeout on DMA completion, buffer stat %04x\n", SPD_REG16(0x38));
798 M_PRINTF("Error: istat %x, ienable %x\n", SPD_REG16(SPD_R_INTR_STAT), SPD_REG16(SPD_R_INTR_MASK));
799 res = ATA_RES_ERR_TIMEOUT;
800 }
801 }
802#endif
803#ifdef ATA_USE_AIFDEV9
804 res = -1;
805#endif
806 } else { /* PIO transfers. */
807 stat = ata_hwport->r_control;
808 if ((res = ata_wait_busy()) < 0)
809 goto finish;
810
811 /* Transfer each PIO data block. */
812 while ((int)(--cmd_state->blkcount) != -1) {
813 if ((res = ata_pio_transfer(cmd_state)) < 0)
814 goto finish;
815 if ((res = ata_wait_busy()) < 0)
816 goto finish;
817 }
818 }
819
820 if (res)
821 goto finish;
822
823 /* Wait until the device isn't busy. */
824 if (ata_hwport->r_status & ATA_STAT_BUSY)
825 res = ata_wait_busy();
826 if ((stat = ata_hwport->r_status) & ATA_STAT_ERR) {
827 M_PRINTF("Error: Command error: status 0x%02x, error 0x%02x.\n", stat, sceAtaGetError());
828 /* In v1.04, there was no check for ICRC. */
829 res = (sceAtaGetError() & ATA_ERR_ICRC) ? ATA_RES_ERR_ICRC : ATA_RES_ERR_IO;
830 }
831
832finish:
833 /* The command has completed (with an error or not), so clean things up. */
834 CancelAlarm(&ata_alarm_cb, NULL);
835#ifdef ATA_USE_DEV9
836 /* Turn off the LED. */
837 SpdSetLED(0);
838#endif
839
840 if (res)
841 M_PRINTF("error: ATA failed, %d\n", res);
842
843 return res;
844}
845
846/* Reset the ATA controller/bus. */
847static int ata_bus_reset(void)
848{
849#ifdef ATA_USE_DEV9
850 USE_SPD_REGS;
851 SPD_REG16(SPD_R_IF_CTRL) = SPD_IF_ATA_RESET;
852 DelayThread(100);
853 SPD_REG16(SPD_R_IF_CTRL) = 0; // Not present in v1.04.
854 SPD_REG16(SPD_R_IF_CTRL) = 0x48;
855 DelayThread(3000);
856#endif
857 return ata_wait_busy();
858}
859
860/* Export 5 */
861int sceAtaSoftReset(void)
862{
863#ifdef ATA_USE_DEV9
864 USE_ATA_REGS;
865#endif
866#ifdef ATA_USE_AIFDEV9
867 USE_AIF_ATA_REGS;
868#endif
869
870 if (ata_hwport->r_control & 0x80)
871 return ATA_RES_ERR_NOTREADY;
872
873 /* Disables device interrupt assertion and asserts SRST. */
874 ata_hwport->r_control = 6;
875 DelayThread(100);
876
877 /* Disable ATA interrupts. */
878 ata_hwport->r_control = 2;
879 DelayThread(3000);
880
881 return ata_wait_busy();
882}
883
884/* Export 17 */
885int sceAtaFlushCache(int device)
886{
887 int res;
888
889 if (!(res = sceAtaExecCmd(NULL, 1, 0, 0, 0, 0, 0, (device << 4) & 0xffff, (atad_devinfo[device].lba48 && !ata_dvrp_workaround) ? ATA_C_FLUSH_CACHE_EXT : ATA_C_FLUSH_CACHE)))
890 res = sceAtaWaitResult();
891
892 return res;
893}
894
895/* Export 13 */
896int sceAtaIdle(int device, int period)
897{
898 int res;
899
900 if (!(res = sceAtaExecCmd(NULL, 1, 0, period & 0xff, 0, 0, 0, (device << 4) & 0xffff, ATA_C_IDLE)))
901 res = sceAtaWaitResult();
902
903 return res;
904}
905
906static int ata_device_identify(int device, void *info)
907{
908 int res;
909
910 if (!(res = sceAtaExecCmd(info, 1, 0, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_IDENTIFY_DEVICE)))
911 res = sceAtaWaitResult();
912
913 return res;
914}
915
916static int ata_device_pkt_identify(int device, void *info)
917{
918 int res;
919
920 res = sceAtaExecCmd(info, 1, 0, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_IDENTIFY_PACKET_DEVICE);
921 if (!res)
922 return sceAtaWaitResult();
923 return res;
924}
925
926/* Export 14 */
927int sceAtaGetSceId(int device, void *data)
928{
929 int res;
930
931 if (!(res = sceAtaExecCmd(data, 1, ATA_SCE_IDENTIFY_DRIVE, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)))
932 res = sceAtaWaitResult();
933
934 return res;
935}
936
937static int ata_device_smart_enable(int device)
938{
939 int res;
940
941 if (!(res = sceAtaExecCmd(NULL, 1, ATA_S_SMART_ENABLE_OPERATIONS, 0, 0, 0x4f, 0xc2, (device << 4) & 0xffff, ATA_C_SMART)))
942 res = sceAtaWaitResult();
943
944 return res;
945}
946
947/* Export 16 */
948int sceAtaSmartSaveAttr(int device)
949{
950 int res;
951
952 if (!(res = sceAtaExecCmd(NULL, 1, ATA_S_SMART_SAVE_ATTRIBUTE_VALUES, 0, 0, 0x4f, 0xc2, (device << 4) & 0xffff, ATA_C_SMART)))
953 res = sceAtaWaitResult();
954
955 return res;
956}
957
958/* Export 15 */
959int sceAtaSmartReturnStatus(int device)
960{
961 USE_ATA_REGS;
962 int res;
963
964 res = sceAtaExecCmd(NULL, 1, ATA_S_SMART_RETURN_STATUS, 0, 0, 0x4f, 0xc2, (device << 4) & 0xffff, ATA_C_SMART);
965 if (res)
966 return res;
967
968 res = sceAtaWaitResult();
969 if (res)
970 return res;
971
972 /* Check to see if the report exceeded the threshold. */
973 if (((ata_hwport->r_lcyl & 0xFF) != 0x4f) || ((ata_hwport->r_hcyl & 0xFF) != 0xc2)) {
974 M_PRINTF("Error: SMART report exceeded threshold.\n");
975 return 1;
976 }
977
978 return 0;
979}
980
981/* Set features - set transfer mode. */
982static int ata_device_set_transfer_mode(int device, int type, int mode)
983{
984 int res;
985
986 res = sceAtaExecCmd(NULL, 1, 3, (type | mode) & 0xff, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SET_FEATURES);
987 if (res)
988 return res;
989
990 res = sceAtaWaitResult();
991 if (res)
992 return res;
993
994 switch (type) {
995#ifdef ATA_USE_DEV9
996#ifdef ATA_MWDMA_MODES
997 case ATA_XFER_MODE_MDMA:
998 ata_multiword_dma_mode(mode);
999 break;
1000#endif
1001 case ATA_XFER_MODE_UDMA:
1002 ata_ultra_dma_mode(mode);
1003 break;
1004 case ATA_XFER_MODE_PIO:
1005 ata_pio_mode(mode);
1006 break;
1007#endif
1008#ifdef ATA_USE_AIFDEV9
1009 case ATA_XFER_MODE_PIO:
1010 aif_tune_drive(0, mode);
1011 break;
1012#endif
1013 }
1014
1015 return 0;
1016}
1017
1018/* Export 9 */
1019/* Note: this can only support DMA modes, due to the commands issued. */
1020int sceAtaDmaTransfer(int device, void *buf, u32 lba, u32 nsectors, int dir)
1021{
1022 return ata_device_sector_io64(device, buf, (u64)lba, nsectors, dir);
1023}
1024
1025int ata_device_sector_io64(int device, void *buf, u64 lba, u32 nsectors, int dir)
1026{
1027 USE_SPD_REGS;
1028 int res = 0, retries;
1029 u16 sector, lcyl, hcyl, select, command, len;
1030 u32 chunk;
1031
1032 while (res == 0 && nsectors > 0) {
1033
1034 if (atad_devinfo[device].lba48 && (ata_dvrp_workaround ? (lba >= atad_devinfo[device].total_sectors) : 1)) {
1035 /* Setup for 48-bit LBA. */
1036 chunk = (nsectors > 65536) ? 65536 : nsectors;
1037 len = (u16)chunk; /* 0 means 65536 in the LBA48 sector count register. */
1038
1039 /* Combine bits 24-31 and bits 0-7 of lba into sector. */
1040 sector = ((lba >> 16) & 0xff00) | (lba & 0xff);
1041 lcyl = ((lba >> 24) & 0xff00) | ((lba >> 8) & 0xff);
1042 hcyl = ((lba >> 32) & 0xff00) | ((lba >> 16) & 0xff);
1043
1044 /* In v1.04, LBA was enabled here. */
1045 select = (device << 4) & 0xffff;
1046 command = (dir == 1) ? ATA_C_WRITE_DMA_EXT : ATA_C_READ_DMA_EXT;
1047 } else {
1048 /* Setup for 28-bit LBA. */
1049 chunk = (nsectors > 256) ? 256 : nsectors;
1050 len = (u16)chunk;
1051 sector = lba & 0xff;
1052 lcyl = (lba >> 8) & 0xff;
1053 hcyl = (lba >> 16) & 0xff;
1054
1055 /* In v1.04, LBA was enabled here. */
1056 select = ((device << 4) | ((lba >> 24) & 0xf)) & 0xffff;
1057 command = (dir == 1) ? ATA_C_WRITE_DMA : ATA_C_READ_DMA;
1058 }
1059
1060 for (retries = 3; retries > 0; retries--) {
1061#ifdef ATA_USE_DEV9
1062#ifdef ATA_GAMESTAR_WORKAROUND
1063 /* Due to the retry loop, put this call (for the GameStar workaround) here instead of the old location. */
1064 if (ata_gamestar_workaround)
1065 ata_set_dir(dir);
1066#endif
1067#endif
1068
1069 if ((res = sceAtaExecCmd(buf, chunk, 0, len, sector, lcyl, hcyl, select, command)) != 0)
1070 break;
1071
1072#ifdef ATA_USE_DEV9
1073#ifdef ATA_GAMESTAR_WORKAROUND
1074 if (!ata_gamestar_workaround)
1075 ata_set_dir(dir);
1076#else
1077 /* Set up (part of) the transfer here. In v1.04, this was called at the top of the outer loop. */
1078 ata_set_dir(dir);
1079#endif
1080#endif
1081
1082 res = sceAtaWaitResult();
1083
1084 /* In v1.04, this was not done. Neither was there a mechanism to retry if a non-permanent error occurs. */
1085 SPD_REG16(SPD_R_IF_CTRL) &= ~SPD_IF_DMA_ENABLE;
1086
1087 if (res != ATA_RES_ERR_ICRC)
1088 break;
1089 }
1090
1091 buf = (void *)((u8 *)buf + chunk * 512);
1092 lba += chunk;
1093 nsectors -= chunk;
1094 }
1095
1096 return res;
1097}
1098
1099static void ata_get_security_status(int device, ata_devinfo_t *devinfo, u16 *param)
1100{
1101 if (ata_device_identify(device, param) == 0)
1102 devinfo[device].security_status = param[ATA_ID_SECURITY_STATUS];
1103}
1104
1105/* Export 10 */
1106int sceAtaSecuritySetPassword(int device, void *password)
1107{
1108 ata_devinfo_t *devinfo = atad_devinfo;
1109 u16 *param = ata_param;
1110 int res;
1111
1112 if (devinfo[device].security_status & ATA_F_SEC_ENABLED)
1113 return 0;
1114
1115 memset(param, 0, 512);
1116 memcpy(param + 1, password, 32);
1117
1118 res = sceAtaExecCmd(param, 1, ATA_SCE_SECURITY_SET_PASSWORD, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL);
1119 if (res == 0)
1120 res = sceAtaWaitResult();
1121
1122 ata_get_security_status(device, devinfo, param);
1123 return res;
1124}
1125
1126/* Export 11 */
1127int sceAtaSecurityUnLock(int device, void *password)
1128{
1129 ata_devinfo_t *devinfo = atad_devinfo;
1130 u16 *param = ata_param;
1131 int res;
1132
1133 if (!(devinfo[device].security_status & ATA_F_SEC_LOCKED))
1134 return 0;
1135
1136 memset(param, 0, 512);
1137 memcpy(param + 1, password, 32);
1138
1139 if ((res = sceAtaExecCmd(param, 1, ATA_SCE_SECURITY_UNLOCK, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)) != 0)
1140 return res;
1141 if ((res = sceAtaWaitResult()) != 0)
1142 return res;
1143
1144 /* Check to see if the drive was actually unlocked. */
1145 ata_get_security_status(device, devinfo, param);
1146 if (devinfo[device].security_status & ATA_F_SEC_LOCKED)
1147 return ATA_RES_ERR_LOCKED;
1148
1149 return 0;
1150}
1151
1152/* Export 12 */
1153int sceAtaSecurityEraseUnit(int device)
1154{
1155 ata_devinfo_t *devinfo = atad_devinfo;
1156 int res;
1157
1158 if (!(devinfo[device].security_status & ATA_F_SEC_ENABLED) || !(devinfo[device].security_status & ATA_F_SEC_LOCKED))
1159 return 0;
1160
1161 /* First send the mandatory ERASE PREPARE command. */
1162 if ((res = sceAtaExecCmd(NULL, 1, ATA_SCE_SECURITY_ERASE_PREPARE, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)) != 0)
1163 goto finish;
1164 if ((res = sceAtaWaitResult()) != 0)
1165 goto finish;
1166
1167 if ((res = sceAtaExecCmd(NULL, 1, ATA_SCE_SECURITY_ERASE_UNIT, 0, 0, 0, 0, (device << 4) & 0xffff, ATA_C_SCE_SECURITY_CONTROL)) == 0)
1168 res = sceAtaWaitResult();
1169
1170finish:
1171 ata_get_security_status(device, devinfo, NULL);
1172 return res;
1173}
1174
1175static void ata_device_probe(ata_devinfo_t *devinfo)
1176{
1177#ifdef ATA_USE_DEV9
1178 USE_ATA_REGS;
1179#endif
1180#ifdef ATA_USE_AIFDEV9
1181 USE_AIF_ATA_REGS;
1182#endif
1183 u16 nsector, sector, lcyl, hcyl;
1184
1185 devinfo->exists = 0;
1186 devinfo->has_packet = 2;
1187
1188 if (ata_hwport->r_control & 0x88)
1189 return;
1190
1191 nsector = ata_hwport->r_nsector & 0xff;
1192 sector = ata_hwport->r_sector & 0xff;
1193 lcyl = ata_hwport->r_lcyl & 0xff;
1194 hcyl = ata_hwport->r_hcyl & 0xff;
1195 (void)ata_hwport->r_select;
1196
1197 if ((nsector != 1) || (sector != 1))
1198 return;
1199 devinfo->exists = 1;
1200
1201 if ((lcyl == 0x00) && (hcyl == 0x00))
1202 devinfo->has_packet = 0;
1203 else if ((lcyl == 0x14) && (hcyl == 0xeb))
1204 devinfo->has_packet = 1;
1205
1206 /* Seems to be for ensuring that there is a device connected.
1207 Not sure why this has to be done, but is present in v2.4. */
1208 ata_hwport->r_lcyl = 0x55;
1209 ata_hwport->r_hcyl = 0xaa;
1210 lcyl = ata_hwport->r_lcyl & 0xff;
1211 hcyl = ata_hwport->r_hcyl & 0xff;
1212
1213 if ((lcyl != 0x55) || (hcyl != 0xaa))
1214 devinfo->exists = 0;
1215}
1216
1217static int ata_init_devices(ata_devinfo_t *devinfo)
1218{
1219#ifdef ATA_USE_DEV9
1220 USE_ATA_REGS;
1221#endif
1222#ifdef ATA_USE_AIFDEV9
1223 USE_AIF_ATA_REGS;
1224#endif
1225 int i, res;
1226 u32 total_sectors_nonlba48, total_sectors_lba48;
1227
1228 /* Probe devices */
1229 if (!ata_dvrp_workaround) {
1230 for (i = 0; i < 2; i++) {
1231 if ((res = sceAtaSoftReset()) != 0)
1232 return res;
1233
1234 ata_device_select(i);
1235 if (ata_hwport->r_control & 0xff)
1236 ata_device_probe(&devinfo[i]);
1237 else
1238 devinfo[i].exists = 0;
1239 }
1240 } else {
1241 if ((res = sceAtaSoftReset()) != 0)
1242 return res;
1243
1244 ata_device_probe(&devinfo[0]);
1245 }
1246
1247 if (!devinfo[0].exists) {
1248 M_PRINTF("Error: Unable to detect HDD 0.\n");
1249 devinfo[1].exists = 0;
1250 return ATA_RES_ERR_NODEV; // Returns 0 in v1.04.
1251 }
1252
1253 if (ata_dvrp_workaround) {
1254 /* If there is a device 1, grab it's info too. */
1255 if ((res = ata_device_select(1)) != 0)
1256 return res;
1257 if (ata_hwport->r_control & 0xff)
1258 ata_device_probe(&devinfo[1]);
1259 else
1260 devinfo[1].exists = 0;
1261 }
1262
1263#ifdef ATA_USE_DEV9
1264 ata_pio_mode(0); // PIO mode is set here, in late ATAD versions.
1265#endif
1266
1267 for (i = 0; i < 2; i++) {
1268 if (!devinfo[i].exists)
1269 continue;
1270
1271 /* Send the IDENTIFY DEVICE command. if it doesn't succeed
1272 devinfo is disabled. */
1273 if (!devinfo[i].has_packet) {
1274 res = ata_device_identify(i, ata_param);
1275 devinfo[i].exists = (res == 0);
1276 } else if (devinfo[i].has_packet == 1) {
1277 /* If it's a packet device, send the IDENTIFY PACKET
1278 DEVICE command. */
1279 res = ata_device_pkt_identify(i, ata_param);
1280 devinfo[i].exists = (res == 0);
1281 }
1282 /* Otherwise, do nothing if has_packet = 2. */
1283
1284 /* This next section is HDD-specific: if no device or it's a
1285 packet (ATAPI) device, we're done. */
1286 if (!devinfo[i].exists || devinfo[i].has_packet)
1287 continue;
1288
1289 /* This section is to detect whether the HDD supports 48-bit LBA
1290 (IDENITFY DEVICE bit 10 word 83) and get the total sectors from
1291 either words(61:60) for 28-bit or words(103:100) for 48-bit. */
1292 devinfo[i].lba48 = (ata_param[ATA_ID_COMMAND_SETS_SUPPORTED] & 0x0400) != 0;
1293
1294 /* Save the total sector counts before we overwrite ata_param with the value of Sony identify drive command. */
1295 total_sectors_nonlba48 = (ata_param[ATA_ID_SECTOTAL_HI] << 16) | ata_param[ATA_ID_SECTOTAL_LO];
1296 if (ata_param[ATA_ID_48BIT_SECTOTAL_HI]) {
1297 total_sectors_lba48 = 0xffffffff;
1298 } else {
1299 total_sectors_lba48 = (ata_param[ATA_ID_48BIT_SECTOTAL_MI] << 16) | ata_param[ATA_ID_48BIT_SECTOTAL_LO];
1300 }
1301
1302 devinfo[i].security_status = ata_param[ATA_ID_SECURITY_STATUS];
1303
1304#ifdef ATA_USE_DEV9
1305 u8 maxUDMA = 4;
1306#ifdef ATA_ENABLE_MAXUDMA
1307 maxUDMA = 6;
1308#endif
1309
1310 /* Ultra DMA mode 4. */
1311 u8 udmaMode = 4;
1312 /* Check the highest UDMA mode supported */
1313 for (int j = maxUDMA; j >= 0; j--) {
1314 /* Check if the current UDMA mode is supported, store it and exit from the loop. */
1315 if (((ata_param[ATA_ID_UDMA_CONTROL] & 0xFF) & (1 << j)) != 0) {
1316 udmaMode = j;
1317 break;
1318 }
1319 }
1320 ata_device_set_transfer_mode(i, ATA_XFER_MODE_UDMA, udmaMode);
1321#endif
1322#ifdef ATA_USE_AIFDEV9
1323 /* PIO mode 4. */
1324 ata_device_set_transfer_mode(i, ATA_XFER_MODE_PIO, 4);
1325#endif
1326 ata_device_smart_enable(i);
1327 /* Set standby timer to 21min 15s. */
1328 sceAtaIdle(i, 0xff);
1329
1330 if (devinfo[i].lba48) {
1331 /* If this device is emulated through the DVRP, use the non-48-bit LBA size. */
1332 if (ata_dvrp_workaround) {
1333 devinfo[i].total_sectors = total_sectors_nonlba48;
1334 /* Check for "PS2LBA48" magic in reserved words 121-124 */
1335 /* PS2 area size is still stored in the 28-bit LBA size */
1336 if (ata_param[121] == 0x4456 &&
1337 ata_param[122] == 0x524c &&
1338 ata_param[123] == 0x4241 &&
1339 ata_param[124] == 0x3438) {
1340 M_PRINTF("LBA48-capable DVRP firmware detected, disabling the workaround\n");
1341 ata_dvrp_workaround = 0;
1342 devinfo[i].total_sectors_lba48 = total_sectors_nonlba48;
1343 } else {
1344 devinfo[i].total_sectors_lba48 = total_sectors_lba48;
1345 }
1346 } else {
1347 devinfo[i].total_sectors = total_sectors_lba48;
1348 devinfo[i].total_sectors_lba48 = total_sectors_lba48;
1349 }
1350 } else {
1351 devinfo[i].total_sectors = total_sectors_nonlba48;
1352 devinfo[i].total_sectors_lba48 = total_sectors_nonlba48;
1353 }
1354
1355 /* Call the proprietary identify command. */
1356#ifdef ATA_SCE_AUTH_HDD
1357 if (sceAtaGetSceId(i, ata_param) != 0) {
1358 M_PRINTF("error: This is not SCE genuine HDD.\n");
1359 memset(&devinfo[i], 0, sizeof(devinfo[i]));
1360 }
1361#endif
1362
1363#ifdef ATA_ENABLE_BDM
1364 g_ata_bd[i].sectorCount = devinfo[i].total_sectors_lba48;
1365 bdm_connect_bd(&g_ata_bd[i]);
1366#endif
1367 }
1368 return 0;
1369}
1370
1371/* Export 4 */
1372ata_devinfo_t *sceAtaInit(int device)
1373{
1374 if (!ata_devinfo_init) {
1375 ata_devinfo_init = 1;
1376 if (ata_bus_reset() || ata_init_devices(atad_devinfo))
1377 return NULL;
1378 }
1379
1380 return &atad_devinfo[device];
1381}
1382
1383#ifdef ATA_USE_DEV9
1384static void ata_set_dir(int dir)
1385{
1386 USE_SPD_REGS;
1387 u16 val;
1388
1389 SPD_REG16(0x38) = 3;
1390 val = SPD_REG16(SPD_R_IF_CTRL) & 1;
1391 val |= (dir == ATA_DIR_WRITE) ? 0x4c : 0x4e;
1392 SPD_REG16(SPD_R_IF_CTRL) = val;
1393#ifdef ATA_GAMESTAR_WORKAROUND
1394 SPD_REG16(SPD_R_XFR_CTRL) = dir | (ata_gamestar_workaround ? 0x86 : 0x6);
1395#else
1396 SPD_REG16(SPD_R_XFR_CTRL) = dir | 0x6; // In v1.04, DMA was enabled here (0x86 instead of 0x6)
1397#endif
1398}
1399
1400static void ata_pio_mode(int mode)
1401{
1402 USE_SPD_REGS;
1403 (void)mode;
1404#ifdef ATA_ALL_PIO_MODES
1405 u16 val;
1406
1407 switch (mode) {
1408 case 1:
1409 val = 0x72;
1410 break;
1411 case 2:
1412 val = 0x32;
1413 break;
1414 case 3:
1415 val = 0x24;
1416 break;
1417 case 4:
1418 val = 0x23;
1419 break;
1420 default:
1421 val = 0x92;
1422 }
1423
1424 SPD_REG16(SPD_R_PIO_MODE) = val;
1425#else
1426 /* In the late ATAD versions, PIO mode 0 is always used if PIO mode is utilized. */
1427 SPD_REG16(SPD_R_PIO_MODE) = 0x92;
1428#endif
1429}
1430
1431#ifdef ATA_MWDMA_MODES
1432static void ata_multiword_dma_mode(int mode)
1433{
1434 USE_SPD_REGS;
1435 u16 val;
1436
1437 switch (mode) {
1438 case 1:
1439 val = 0x45;
1440 break;
1441 case 2:
1442 val = 0x24;
1443 break;
1444 default:
1445 val = 0xff;
1446 }
1447
1448 SPD_REG16(SPD_R_MWDMA_MODE) = val;
1449 SPD_REG16(SPD_R_IF_CTRL) = (SPD_REG16(SPD_R_IF_CTRL) & 0xfffe) | 0x48;
1450}
1451#endif
1452
1453static void ata_ultra_dma_mode(int mode)
1454{
1455 USE_SPD_REGS;
1456 u16 val;
1457
1458 switch (mode) {
1459 case 1:
1460 val = 0x85;
1461 break;
1462 case 2:
1463 val = 0x63;
1464 break;
1465 case 3:
1466 val = 0x62;
1467 break;
1468 case 4:
1469 val = 0x61;
1470 break;
1471 default:
1472 val = 0xa7;
1473 }
1474
1475 SPD_REG16(SPD_R_UDMA_MODE) = val;
1476 SPD_REG16(SPD_R_IF_CTRL) |= 0x49;
1477}
1478#endif
1479
1480#ifdef ATA_USE_AIFDEV9
1481static void aif_tune_drive(int unit, int mode)
1482{
1483 USE_AIF_REGS;
1484 unsigned int use_iordy, value;
1485
1486 use_iordy = 1;
1487 value = (use_iordy << 3) | mode;
1488 M_PRINTF("AIF HDD: tune unit%d, mode=%u\n", unit, value);
1489
1490 switch (unit) {
1491 case 0:
1492 aif_regs[AIF_ATA_TCFG] = (aif_regs[AIF_ATA_TCFG] & 0xf0) + value;
1493 break;
1494 case 1:
1495 aif_regs[AIF_ATA_TCFG] = (aif_regs[AIF_ATA_TCFG] & 0x0f) + (value << 4);
1496 break;
1497 }
1498}
1499#endif
1500
1501/* Export 18 */
1502int sceAtaIdleImmediate(int device)
1503{
1504 int res;
1505
1506 if (!(res = sceAtaExecCmd(NULL, 1, 0, 0, 0, 0, 0, (device << 4) & 0xFFFF, ATA_C_IDLE_IMMEDIATE)))
1507 res = sceAtaWaitResult();
1508
1509 return res;
1510}
1511
1512static int ata_device_standby_immediate(int device)
1513{
1514 int res;
1515
1516 if (!(res = sceAtaExecCmd(NULL, 1, 0, 0, 0, 0, 0, (device << 4) & 0xFFFF, ATA_C_STANDBY_IMMEDIATE)))
1517 res = sceAtaWaitResult();
1518
1519 return res;
1520}
1521
1522static void ata_shutdown_cb(void)
1523{
1524 int i;
1525
1526 for (i = 0; i < 2; i++) {
1527 if (atad_devinfo[i].exists)
1528 ata_device_standby_immediate(i);
1529 }
1530}
1531
1532#ifdef ATA_ENABLE_BDM
1533//
1534// Block device interface
1535//
1536static int ata_bd_read(struct block_device *bd, u64 sector, void *buffer, u16 count)
1537{
1538 if (ata_device_sector_io64(bd->devNr, buffer, sector, count, ATA_DIR_READ) != 0) {
1539 return -EIO;
1540 }
1541
1542 return count;
1543}
1544
1545static int ata_bd_write(struct block_device *bd, u64 sector, const void *buffer, u16 count)
1546{
1547 if (ata_device_sector_io64(bd->devNr, (void *)buffer, sector, count, ATA_DIR_WRITE) != 0) {
1548 return -EIO;
1549 }
1550
1551 return count;
1552}
1553
1554static void ata_bd_flush(struct block_device *bd)
1555{
1556 sceAtaFlushCache(bd->devNr);
1557}
1558
1559static int ata_bd_stop(struct block_device *bd)
1560{
1561 ata_device_standby_immediate(bd->devNr);
1562
1563 return 0;
1564}
1565#endif
EIO
#define EIO
Definition errno.h:38
_ata_cmd_info
Definition ps2atad.c:88
_ata_cmd_state
Definition ps2atad.c:177
_ata_devinfo::security_status
u32 security_status
Definition atad.h:36
_ata_devinfo::lba48
u32 lba48
Definition atad.h:38
_ata_devinfo::exists
s32 exists
Definition atad.h:30
_ata_devinfo::total_sectors
u32 total_sectors
Definition atad.h:34
_ata_devinfo::has_packet
s32 has_packet
Definition atad.h:32
_ata_devinfo::total_sectors_lba48
u32 total_sectors_lba48
Definition atad.h:40
block_device
Definition bdm.h:23
iop_event_t
Definition thevent.h:39
irx_export_table
Definition irx.h:117
EA_SINGLE
#define EA_SINGLE
Definition thevent.h:34
count
u32 count
start sector of fragmented bd/file
Definition usbhdfsd-common.h:1