intrman.h

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/*
# _____     ___ ____     ___ ____
#  ____|   |    ____|   |        | |____|
# |     ___|   |____ ___|    ____| |    \    PS2DEV Open Source Project.
#-----------------------------------------------------------------------
# Copyright (c) 2003 Marcus R. Brown <mrbrown@0xd6.org>
# Licenced under Academic Free License version 2.0
# Review ps2sdk README & LICENSE files for further details.
*/

 
#ifndef __INTRMAN_H__
#define __INTRMAN_H__
 
#include <types.h>
#include <irx.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
enum iop_irq_list {
    IOP_IRQ_VBLANK = 0,
    IOP_IRQ_SBUS,
    IOP_IRQ_CDVD,
    IOP_IRQ_DMA,
    IOP_IRQ_RTC0,
    IOP_IRQ_RTC1,
    IOP_IRQ_RTC2,
    IOP_IRQ_SIO0,
    IOP_IRQ_SIO1,
    IOP_IRQ_SPU,
    IOP_IRQ_PIO,
    IOP_IRQ_EVBLANK,
    IOP_IRQ_DVD,
    IOP_IRQ_DEV9,
    IOP_IRQ_RTC3,
    IOP_IRQ_RTC4,
    IOP_IRQ_RTC5,
    IOP_IRQ_SIO2,
    IOP_IRQ_HTR0,
    IOP_IRQ_HTR1,
    IOP_IRQ_HTR2,
    IOP_IRQ_HTR3,
    IOP_IRQ_USB,
    IOP_IRQ_EXTR,
    IOP_IRQ_ILINK,
    IOP_IRQ_FDMA,
 
    IOP_IRQ_DMA_MDEC_IN = 0x20,
    IOP_IRQ_DMA_MDEC_OUT,
    IOP_IRQ_DMA_SIF2,
    IOP_IRQ_DMA_CDVD,
    IOP_IRQ_DMA_SPU,
    IOP_IRQ_DMA_PIO,
    IOP_IRQ_DMA_GPU_OTC,
    IOP_IRQ_DMA_BERR,
    IOP_IRQ_DMA_SPU2,
    IOP_IRQ_DMA_DEV9,
    IOP_IRQ_DMA_SIF0,
    IOP_IRQ_DMA_SIF1,
    IOP_IRQ_DMA_SIO2_IN,
    IOP_IRQ_DMA_SIO2_OUT,

    IOP_IRQ_SW1 = 0x3E,
    IOP_IRQ_SW2
};
 
typedef struct intrman_intr_handler_data_
{
    int (*handler)(void *userdata);
    void *userdata;
} intrman_intr_handler_data_t;
 
typedef struct intrman_internals_
{
    intrman_intr_handler_data_t *interrupt_handler_table;
    int masked_icr_1;
    int masked_icr_2;
    int dmac2_interrupt_handler_mask;
} intrman_internals_t;
 
extern intrman_internals_t *GetIntrmanInternalData(void);

extern int RegisterIntrHandler(int irq, int mode, int (*handler)(void *arg), void *arg);

extern int ReleaseIntrHandler(int irq);

extern int EnableIntr(int irq);

extern int DisableIntr(int irq, int *res);

extern int CpuDisableIntr();
extern int CpuEnableIntr();

extern int CpuSuspendIntr(int *state);

extern int CpuResumeIntr(int state);

extern int CpuInvokeInKmode(void *function, ...);

extern void DisableDispatchIntr(int irq);
extern void EnableDispatchIntr(int irq);

extern int QueryIntrContext(void);

extern int QueryIntrStack(void *sp);
 
extern int iCatchMultiIntr(void);

extern void SetNewCtxCb(void *cb);
extern void ResetNewCtxCb(void);
extern void SetShouldPreemptCb(void *cb);
extern void ResetShouldPreemptCb(void);
 
#define intrman_IMPORTS_start DECLARE_IMPORT_TABLE(intrman, 1, 2)
#define intrman_IMPORTS_end   END_IMPORT_TABLE
 
#define I_GetIntrmanInternalData DECLARE_IMPORT(3, GetIntrmanInternalData)
#define I_RegisterIntrHandler    DECLARE_IMPORT(4, RegisterIntrHandler)
#define I_ReleaseIntrHandler     DECLARE_IMPORT(5, ReleaseIntrHandler)
#define I_EnableIntr             DECLARE_IMPORT(6, EnableIntr)
#define I_DisableIntr            DECLARE_IMPORT(7, DisableIntr)
#define I_CpuDisableIntr         DECLARE_IMPORT(8, CpuDisableIntr)
#define I_CpuEnableIntr          DECLARE_IMPORT(9, CpuEnableIntr)
#define I_CpuInvokeInKmode       DECLARE_IMPORT(14, CpuInvokeInKmode);
#define I_DisableDispatchIntr    DECLARE_IMPORT(15, DisableDispatchIntr);
#define I_EnableDispatchIntr     DECLARE_IMPORT(16, EnableDispatchIntr);
#define I_CpuSuspendIntr         DECLARE_IMPORT(17, CpuSuspendIntr)
#define I_CpuResumeIntr          DECLARE_IMPORT(18, CpuResumeIntr)
#define I_QueryIntrContext       DECLARE_IMPORT(23, QueryIntrContext)
#define I_QueryIntrStack         DECLARE_IMPORT(24, QueryIntrStack)
#define I_iCatchMultiIntr        DECLARE_IMPORT(25, iCatchMultiIntr)
#define I_SetNewCtxCb            DECLARE_IMPORT(28, SetNewCtxCb)
#define I_SetShouldPreemptCb     DECLARE_IMPORT(30, SetShouldPreemptCb)
 
/* For compatibility purposes */
#define INUM_VBLANK IOP_IRQ_VBLANK
#define INUM_GM IOP_IRQ_SBUS
#define INUM_CDROM IOP_IRQ_CDVD
#define INUM_DMA IOP_IRQ_DMA
#define INUM_RTC0 IOP_IRQ_RTC0
#define INUM_RTC1 IOP_IRQ_RTC1
#define INUM_RTC2 IOP_IRQ_RTC2
#define INUM_SIO0 IOP_IRQ_SIO0
#define INUM_SIO1 IOP_IRQ_SIO1
#define INUM_SPU IOP_IRQ_SPU
#define INUM_PIO IOP_IRQ_PIO
#define INUM_EVBLANK IOP_IRQ_EVBLANK
#define INUM_DVD IOP_IRQ_DVD
#define INUM_PCMCIA IOP_IRQ_DEV9
#define INUM_RTC3 IOP_IRQ_RTC3
#define INUM_RTC4 IOP_IRQ_RTC4
#define INUM_RTC5 IOP_IRQ_RTC5
#define INUM_SIO2 IOP_IRQ_SIO2
#define INUM_HTR0 IOP_IRQ_HTR0
#define INUM_HTR1 IOP_IRQ_HTR1
#define INUM_HTR2 IOP_IRQ_HTR2
#define INUM_HTR3 IOP_IRQ_HTR3
#define INUM_USB IOP_IRQ_USB
#define INUM_EXTR IOP_IRQ_EXTR
#define INUM_FWRE IOP_IRQ_ILINK
#define INUM_FDMA IOP_IRQ_FDMA
#define INUM_DMA_0 IOP_IRQ_DMA_MDEC_IN
#define INUM_DMA_1 IOP_IRQ_DMA_MDEC_OUT
#define INUM_DMA_2 IOP_IRQ_DMA_SIF2
#define INUM_DMA_3 IOP_IRQ_DMA_CDVD
#define INUM_DMA_4 IOP_IRQ_DMA_SPU
#define INUM_DMA_5 IOP_IRQ_DMA_PIO
#define INUM_DMA_6 IOP_IRQ_DMA_GPU_OTC
#define INUM_DMA_BERR IOP_IRQ_DMA_BERR
#define INUM_DMA_7 IOP_IRQ_DMA_SPU2
#define INUM_DMA_8 IOP_IRQ_DMA_DEV9
#define INUM_DMA_9 IOP_IRQ_DMA_SIF0
#define INUM_DMA_10 IOP_IRQ_DMA_SIF1
#define INUM_DMA_11 IOP_IRQ_DMA_SIO2_IN
#define INUM_DMA_12 IOP_IRQ_DMA_SIO2_OUT
 
#define SetCtxSwitchHandler(...) SetNewCtxCb(__VA_ARGS__)
#define ResetCtxSwitchHandler(...) ResetNewCtxCb(__VA_ARGS__)
#define SetCtxSwitchReqHandler(...) SetShouldPreemptCb(__VA_ARGS__)
#define ResetCtxSwitchReqHandler(...) ResetShouldPreemptCb(__VA_ARGS__)
 
#ifdef __cplusplus
}
#endif
 
#endif /* __INTRMAN_H__ */