sdk-core v2026.11.05
PS2 SDK - core tier (build-critical EE/IOP modules)
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dmacman.h
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1/*
2# _____ ___ ____ ___ ____
3# ____| | ____| | | |____|
4# | ___| |____ ___| ____| | \ PS2DEV Open Source Project.
5#-----------------------------------------------------------------------
6# Copyright (c) 2003 Marcus R. Brown <mrbrown@0xd6.org>
7# Licenced under Academic Free License version 2.0
8# Review ps2sdk README & LICENSE files for further details.
9*/
10
16
17#ifndef __DMACMAN_H__
18#define __DMACMAN_H__
19
20#include <types.h>
21#include <irx.h>
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27typedef struct _iop_dmac_chan {
28 u32 madr;
29 u32 bcr;
30 u32 chcr;
31} iop_dmac_chan_t;
32
33/* CHCR flags */
34#define DMAC_CHCR_30 (1<<30)
36#define DMAC_CHCR_TR (1<<24)
38#define DMAC_CHCR_LI (1<<10)
40#define DMAC_CHCR_CO (1<<9)
41#define DMAC_CHCR_08 (1<<8)
43#define DMAC_CHCR_DR (1<<0)
44
45#define DMAC_TO_MEM 0
46#define DMAC_FROM_MEM 1
47
48//SIF2 DMA ch 2 (GPU)
49#define IOP_DMAC_SIF2_MADR (*(volatile int*)0xBF8010A0)
50#define IOP_DMAC_SIF2_BCR (*(volatile int*)0xBF8010A4)
51#define IOP_DMAC_SIF2_BCR_size (*(volatile short*)0xBF8010A4)
52#define IOP_DMAC_SIF2_BCR_count (*(volatile short*)0xBF8010A6)
53#define IOP_DMAC_SIF2_CHCR (*(volatile int*)0xBF8010A8)
54//SIF0 DMA ch 9
55#define IOP_DMAC_SIF9_MADR (*(volatile int*)0xBF801520)
56#define IOP_DMAC_SIF9_BCR (*(volatile int*)0xBF801524)
57#define IOP_DMAC_SIF9_BCR_size (*(volatile short*)0xBF801524)
58#define IOP_DMAC_SIF9_BCR_count (*(volatile short*)0xBF801526)
59#define IOP_DMAC_SIF9_CHCR (*(volatile int*)0xBF801528)
60#define IOP_DMAC_SIF9_TADR (*(volatile int*)0xBF80152C)
61//SIF1 DMA ch 10 (0xA)
62#define IOP_DMAC_SIFA_MADR (*(volatile int*)0xBF801530)
63#define IOP_DMAC_SIFA_BCR (*(volatile int*)0xBF801534)
64#define IOP_DMAC_SIFA_BCR_size (*(volatile short*)0xBF801534)
65#define IOP_DMAC_SIFA_BCR_count (*(volatile short*)0xBF801536)
66#define IOP_DMAC_SIFA_CHCR (*(volatile int*)0xBF801538)
67
68#define IOP_DMAC_DPCR (*(volatile int*)0xBF8010F0)
69#define IOP_DMAC_DPCR2 (*(volatile int*)0xBF801570)
70
71enum _iop_dmac_ch {
72 IOP_DMAC_MDECin, IOP_DMAC_MDECout, IOP_DMAC_SIF2, IOP_DMAC_CDVD,
73 IOP_DMAC_SPU, IOP_DMAC_PIO, IOP_DMAC_OTC, IOP_DMAC_SPU2,
74 IOP_DMAC_DEV9, IOP_DMAC_SIF0, IOP_DMAC_SIF1, IOP_DMAC_SIO2in,
75 IOP_DMAC_SIO2out, IOP_DMAC_FDMA0, IOP_DMAC_FDMA1, IOP_DMAC_FDMA2,
76 IOP_DMAC_CPU = 67, //'C'
77 IOP_DMAC_USB = 85, //'U'
78};
79
80/* Note that these are far from official names. */
81
82/* Memory ADdRess */
83extern void dmac_ch_set_madr(u32 channel, u32 val);
84extern u32 dmac_ch_get_madr(u32 channel);
85
86/* Block Control Register */
87extern void dmac_ch_set_bcr(u32 channel, u32 val);
88extern u32 dmac_ch_get_bcr(u32 channel);
89
90/* CHannel Control Register */
91extern void dmac_ch_set_chcr(u32 channel, u32 val);
92extern u32 dmac_ch_get_chcr(u32 channel);
93
94/* Tag ADdRess */
95extern void dmac_ch_set_tadr(u32 channel, u32 val);
96extern u32 dmac_ch_get_tadr(u32 channel);
97
98extern void dmac_set_4_9_a(u32 channel, u32 val);
99extern u32 dmac_get_4_9_a(u32 channel);
100
101/* Dmac P??? Control Registers */
102extern void dmac_set_dpcr(u32 val);
103extern u32 dmac_get_dpcr(void);
104extern void dmac_set_dpcr2(u32 val);
105extern u32 dmac_get_dpcr2(void);
106extern void dmac_set_dpcr3(u32 val);
107extern u32 dmac_get_dpcr3(void);
108
109/* Dmac Interrupt Control Registers */
110extern void dmac_set_dicr(u32 val);
111extern u32 dmac_get_dicr(void);
112extern void dmac_set_dicr2(u32 val);
113extern u32 dmac_get_dicr2(void);
114
115extern void dmac_set_BF80157C(u32 val);
116extern u32 dmac_get_BF80157C(void);
117
118extern void dmac_set_BF801578(u32 val);
119extern u32 dmac_get_BF801578(void);
120
121/* Initialize the given channel and start the transfer. Returns 1 if the
122 transfer was started, and 0 on error. */
123extern int sceSetSliceDMA(u32 channel, void * addr, u32 size, u32 count, int dir);
124
125extern int dmac_set_dma_chained_spu_sif0(u32 channel, u32 size, u32 tadr);
126extern int dmac_set_dma_sif0(u32 channel, u32 size, u32 tadr);
127extern int dmac_set_dma_sif1(u32 ch, u32 size);
128
129/* Start a transfer on the given channel. */
130extern void sceStartDMA(u32 channel);
131
132/* Set the DPCRn value for a specific channel. */
133extern void sceSetDMAPriority(u32 channel, u32 val);
134
135extern void sceEnableDMAChannel(u32 channel);
136extern void sceDisableDMAChannel(u32 channel);
137
138#define dmacman_IMPORTS_start DECLARE_IMPORT_TABLE(dmacman, 1, 1)
139#define dmacman_IMPORTS_end END_IMPORT_TABLE
140
141#define I_dmac_ch_set_madr DECLARE_IMPORT(4, dmac_ch_set_madr)
142#define I_dmac_ch_get_madr DECLARE_IMPORT(5, dmac_ch_get_madr)
143#define I_dmac_ch_set_bcr DECLARE_IMPORT(6, dmac_ch_set_bcr)
144#define I_dmac_ch_get_bcr DECLARE_IMPORT(7, dmac_ch_get_bcr)
145#define I_dmac_ch_set_chcr DECLARE_IMPORT(8, dmac_ch_set_chcr)
146#define I_dmac_ch_get_chcr DECLARE_IMPORT(9, dmac_ch_get_chcr)
147#define I_dmac_ch_set_tadr DECLARE_IMPORT(10, dmac_ch_set_tadr)
148#define I_dmac_ch_get_tadr DECLARE_IMPORT(11, dmac_ch_get_tadr)
149#define I_dmac_set_4_9_a DECLARE_IMPORT(12, dmac_set_4_9_a)
150#define I_dmac_get_4_9_a DECLARE_IMPORT(13, dmac_get_4_9_a)
151#define I_dmac_set_dpcr DECLARE_IMPORT(14, dmac_set_dpcr)
152#define I_dmac_get_dpcr DECLARE_IMPORT(15, dmac_get_dpcr)
153#define I_dmac_set_dpcr2 DECLARE_IMPORT(16, dmac_set_dpcr2)
154#define I_dmac_get_dpcr2 DECLARE_IMPORT(17, dmac_get_dpcr2)
155#define I_dmac_set_dpcr3 DECLARE_IMPORT(18, dmac_set_dpcr3)
156#define I_dmac_get_dpcr3 DECLARE_IMPORT(19, dmac_get_dpcr3)
157#define I_dmac_set_dicr DECLARE_IMPORT(20, dmac_set_dicr)
158#define I_dmac_get_dicr DECLARE_IMPORT(21, dmac_get_dicr)
159#define I_dmac_set_dicr2 DECLARE_IMPORT(22, dmac_set_dicr2)
160#define I_dmac_get_dicr2 DECLARE_IMPORT(23, dmac_get_dicr2)
161#define I_dmac_set_BF80157C DECLARE_IMPORT(24, dmac_set_BF80157C)
162#define I_dmac_get_BF80157C DECLARE_IMPORT(25, dmac_get_BF80157C)
163#define I_dmac_set_BF801578 DECLARE_IMPORT(26, dmac_set_BF801578)
164#define I_dmac_get_BF801578 DECLARE_IMPORT(27, dmac_get_BF801578)
165#define I_sceSetSliceDMA DECLARE_IMPORT(28, sceSetSliceDMA)
166#define I_dmac_set_dma_chained_spu_sif0 DECLARE_IMPORT(29, dmac_set_dma_chained_spu_sif0)
167#define I_dmac_set_dma_sif0 DECLARE_IMPORT(30, dmac_set_dma_sif0)
168#define I_dmac_set_dma_sif1 DECLARE_IMPORT(31, dmac_set_dma_sif1)
169#define I_sceStartDMA DECLARE_IMPORT(32, sceStartDMA)
170#define I_sceSetDMAPriority DECLARE_IMPORT(33, sceSetDMAPriority)
171#define I_sceEnableDMAChannel DECLARE_IMPORT(34, sceEnableDMAChannel)
172#define I_sceDisableDMAChannel DECLARE_IMPORT(35, sceDisableDMAChannel)
173
174// Backwards-compatibility defines
175
176#define dmac_request(...) sceSetSliceDMA(__VA_ARGS__)
177#define dmac_transfer(...) sceStartDMA(__VA_ARGS__)
178#define dmac_ch_set_dpcr(...) sceSetDMAPriority(__VA_ARGS__)
179#define dmac_enable(...) sceEnableDMAChannel(__VA_ARGS__)
180#define dmac_disable(...) sceDisableDMAChannel(__VA_ARGS__)
181
182#define I_dmac_request I_sceSetSliceDMA
183#define I_dmac_transfer I_sceStartDMA
184#define I_dmac_ch_set_dpcr I_sceSetDMAPriority
185#define I_dmac_enable I_sceEnableDMAChannel
186#define I_dmac_disable I_sceDisableDMAChannel
187
188#ifdef __cplusplus
189}
190#endif
191
192#endif /* __DMACMAN_H__ */
_iop_dmac_chan
Definition dmacman.h:27
count
u32 count
start sector of fragmented bd/file
Definition usbhdfsd-common.h:1